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Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew
Conference proceeding

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Baris Taskin and Ivan Kourtev
Proceedings of the 8th ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems, pp 111-118
02 Dec 2002
DOI: https://doi.org/10.1145/589411.589437

Abstract

cycle stealing linear programming clock skew optimization
This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is stand-alone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1].

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