Conference proceeding
Post-CTS Clock Skew Scheduling with Limited Delay Buffering
2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2
01 Jan 2009
Abstract
Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the leaves of the clock tree to implement a limited version of clock skew scheduling. The method suggests the limitation of delay buffering on each clock tree branch as well as a global monitoring of total amount of delay buffering to improve the circuit performance. The delay buffering for non-zero clock skew operation is performed only after the clock sinks in order to preserve the structure and the optimizations implemented with any clock tree synthesis methodology. Experimental results demonstrate the superiority of the proposed post-CTS methodology over previous methods and demonstrate an important trend of clock period improvement over varying upper bounds of delay buffering. It is shown that the majority of the clock period improvement achievable through clock skew scheduling is obtained through very limited buffering (approximate to 43% average improvement through 10% of max buffering).
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Details
- Title
- Post-CTS Clock Skew Scheduling with Limited Delay Buffering
- Creators
- Jianchao Lu - Drexel UniversityBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2
- Series
- Midwest Symposium on Circuits and Systems Conference Proceedings
- Publisher
- IEEE
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000277574000056
- Scopus ID
- 2-s2.0-77950651331
- Other Identifier
- 991019168542604721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Information Systems
- Engineering, Electrical & Electronic