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Practical Performance of Analog Attack Techniques
Conference proceeding

Practical Performance of Analog Attack Techniques

Vaibhav Venugopal Rao, Kyle Juretus and Ioannis Savidis
2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
27 Jun 2022
DOI: https://doi.org/10.1109/HOST54066.2022.9839966

Abstract

Analog circuits Circuit topology Genetic algorithms Hardware Integrated circuits Security Supply chains
The increasing number of vulnerabilities in analog circuits has motivated the development of novel security techniques that protect the analog supply chain. A variety of attacks including ones based on satisfiability modulo theory (SMT) and genetic algorithms (GA) have been executed on different analog circuits to evaluate the vulnerabilities of the added protection. However, the current attack techniques assume ideal conditions, where the attacker has complete knowledge of the IC except for the key used to obfuscate the circuit. In this paper, four different threat models are examined, where an adversary is assumed to have different levels of access to circuit and security information. The analysis of the attack performance on key-based parameter obfuscation is performed premised upon the level of information possessed by the adversary. The analog attack techniques are evaluated on five distinct circuit topologies, each implemented with different key sizes and obfuscated parameters. Through analysis of the results, a characterization of the advantages and disadvantages of the analog attack algorithms is provided.

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Collaboration types
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
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