Conference proceeding
Protecting Analog Circuits with Parameter Biasing Obfuscation
2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017)
01 Jan 2017
Abstract
A methodology to secure analog intellectual property (IP) by obfuscating biasing conditions is presented in this paper. Previous research methodologies have focused on protecting digital IP from theft, overproduction, counterfeiting, and Trojan insertion. Analog IP has not been investigated as it does not share the same replicated structures and functionalities used for digital protection. The bias encryption techniques presented in this paper are implemented on a phase locked loop (PLL). The operating frequency of the PLL is masked in the range of 800 MHz to 2.2 GHz with a 40-bit encryption key. The probability of determining the correct key through brute force attack is 9.095x10(-13). The overheads of encrypting the PLL include a 6.3% increase in active area, a 0.89% increase in power consumption, and a 5 dBc/Hz increase in phase noise.
Metrics
6 Record Views
Details
- Title
- Protecting Analog Circuits with Parameter Biasing Obfuscation
- Creators
- Vaibhav Venugopal Rao - Drexel Univ, Dept Elect & Comp Engn, Philadelphia, PA 19104 USAIoannis Savidis - Drexel UniversityIEEE
- Publication Details
- 2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017)
- Conference
- 2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017), 18th
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Identifiers
- 991019170352704721
InCites Highlights
These are selected metrics from InCites Benchmarking & Analytics tool, related to this output
- Web of Science research areas
- Engineering, Electrical & Electronic