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RAPIDITAS: RAPId Design-space-exploration Incorporating Trace-based Analysis and Simulation
Conference proceeding

RAPIDITAS: RAPId Design-space-exploration Incorporating Trace-based Analysis and Simulation

Amit Kumar Singh, Anup Das and Akash Kumar
16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), pp 836-843
01 Jan 2013

Abstract

Computer Science Computer Science, Theory & Methods Engineering Engineering, Electrical & Electronic Science & Technology Technology
Simulation-based Design Space Exploration (DSE) to evaluate all possible mappings for a given application and Multiprocessor-System-on-Chip (MPSoC) platform is computationally costly for large problems. Even using efficient exploration methodologies to evaluate the mappings cannot overcome the evaluation time bottleneck. This paper presents a novel DSE methodology that analyzes the execution trace to prune the vast design space. Simulations are employed only on the pruned design points (mappings), hence reducing the number of simulations. The methodology performs iterative exploration and provides premier mappings requiring different number of processors, which can be used at run-time subject to desired performance and available platform processors. We evaluate our methodology by using models of real-life multimedia applications and demonstrate that the DSE time is reduced by 72% while generating high quality mappings.

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Web of Science research areas
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
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