Logo image
Back
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis
Conference proceeding   Open access

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis

Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Seyed Aresh Beheshti Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P D, Houman Homayoun, Ioannis Savidis, Liang Zhao, …
Proceedings of the Great Lakes Symposium on VLSI 2022, pp 493-500
06 Jun 2022
DOI: https://doi.org/10.1145/3526241.3530831
url
https://doi.org/10.1145/3526241.3530831View
Published, Version of Record (VoR) Open

Abstract

Computing methodologies -- Machine learning -- Machine learning approaches -- Neural networks Hardware -- Electronic design automation -- Timing analysis -- Static timing analysis
This paper presents RAPTA, a customized Representation-learning Architecture for automation of feature engineering and predicting the result of Path-based Timing-Analysis early in the physical design cycle. RAPTA offers multiple advantages compared to prior work: 1) It has superior accuracy with errors std ranges 3.9ps~16.05ps in 32nm technology. 2) RAPTA's architecture does not change with feature-set size, 3) RAPTA does not require manual input feature engineering. To the best of our knowledge, this is the first work, in which Bidirectional Long Short-Term Memory (Bi-LSTM) representation learning is used to digest raw information for feature engineering, where generation of latent features and Multilayer Perceptron (MLP) based regression for timing prediction can be trained end-to-end.

Metrics

1 Record Views
2 citations in Web of Science

Details

Logo image