Conference proceeding
Reduced overhead gate level logic encryption
2016 International Great Lakes Symposium on VLSI (GLSVLSI), v 18-20-, pp 15-20
May 2016
Abstract
Untrusted third-parties are found throughout the integrated circuit (IC) design flow resulting in potential threats in IC reliability and security. Threats include IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans. Logic encryption has emerged as a method of enhancing security against such threats, however, current implementations of logic encryption, including the XOR or look-up table (LUT) techniques, have high per-gate overheads in area, performance, and power. A novel gate level logic encryption technique with reduced per-gate overheads is described in this paper. In addition, a technique to expand the search space of a key sequence is provided, increasing the difficulty for an adversary to extract the key value. A power reduction of 41.50%, an estimated area reduction of 43.58%, and a performance increase of 34.54% is achieved when using the proposed gate level logic encryption instead of the LUT based technique for an encrypted AND gate.
Metrics
Details
- Title
- Reduced overhead gate level logic encryption
- Creators
- Kyle Juretus - Drexel UniversityIoannis Savidis - Drexel UniversityIEEE
- Publication Details
- 2016 International Great Lakes Symposium on VLSI (GLSVLSI), v 18-20-, pp 15-20
- Conference
- 2016 International Great Lakes Symposium on VLSI (GLSVLSI)
- Publisher
- Association for Computing Machinery (ACM)
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000389775900002
- Scopus ID
- 2-s2.0-84974678489
- Other Identifier
- 991019173870104721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Theory & Methods