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Reducing Logic Locking Key Leakage Through the Scan Chain
Conference proceeding

Reducing Logic Locking Key Leakage Through the Scan Chain

Kyle Juretus, Ioannis Savidis and IEEE
2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
01 Jan 2020
DOI: https://doi.org/10.1109/ISCAS45731.2020.9180707

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A novel technique to secure the scan chain of an integrated circuit (IC) is proposed. The technique creates a logical partition between the functional and test modes of a circuit, where the correct logic locking key is only provided in functional mode. The proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers. The charge accumulation circuit results in a 9.2% increase in area as compared to a minimum sized 180 nm 2-input NAND gate. Implementing the technique on the ISCAS'89 s15850 benchmark circuit results in a 2.87% increase in the total area.

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Web of Science research areas
Engineering, Electrical & Electronic
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