Conference proceeding
Reducing Parity Generation Latency through Input Value Aware Circuits
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, pp 109-112
01 Jan 2009
Abstract
Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper we propose a parity generator circuit design that is capable of generating the parity if the input value is narrow. We show that parity can be generated faster than a regular XOR tree implementation using our design for the values that can be represented using fewer bits.
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3 citations in Scopus
Details
- Title
- Reducing Parity Generation Latency through Input Value Aware Circuits
- Creators
- Yusuf Osmanlioglu - AnkaraY. Onur Kocberber - TOBB University of Economics and TechnologyOguz Ergin - TOBB University of Economics and TechnologyACM
- Publication Details
- GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, pp 109-112
- Publisher
- Assoc Computing Machinery
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Computer Science (Computing)
- Web of Science ID
- WOS:000293808200022
- Scopus ID
- 2-s2.0-70350582595
- Other Identifier
- 991021869013204721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture