Conference proceeding
Register On MEsh (ROME): A novel approach for clock mesh network synthesis
2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp 1219-1222
May 2011
Abstract
A clock mesh network synthesis and optimization flow is proposed which entails the optimal mesh size selection, incremental register placement, mesh reduction and buffer driver insertion. The proposed method is based on incrementally placing the registers on a mesh, which gives the method its name "Register on MEsh (ROME)". The primary objectives of ROME are low global clock skew and power dissipation, which are achieved through a sparse mesh implementation with registers mesh. Experimental results show that the total wirelength on the clock mesh (grid wires and stub wires) is reduced by 36.1% with a 2.8ps clock skew improvement. The total power consumption of the experimented circuits is reduced by 14.1% on average.
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Details
- Title
- Register On MEsh (ROME): A novel approach for clock mesh network synthesis
- Creators
- Jianchao Lu - Drexel UniversityYusuf Aksehir - Sabancı UniversityBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp 1219-1222
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000297265301110
- Scopus ID
- 2-s2.0-79960872535
- Other Identifier
- 991019170544004721
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- Collaboration types
- Domestic collaboration
- International collaboration
- Web of Science research areas
- Engineering, Electrical & Electronic