Conference proceeding
Robust Low Power Clock Synchronization for Multi-Die Systems
2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), v 2019-, pp 1-6
01 Jan 2019
Featured in Collection : UN Sustainable Development Goals @ Drexel
Abstract
A novel clock generation and distribution network is proposed for multi-die architectures connected through an active silicon interposer. The proposed clock network generates and distributes a resonant clock through the active silicon interposer between dies, with each die served through resonant local clock trees. The proposed active silicon interposer rotary oscillator array (AI-ROA) serves to establish a unitary clock domain, providing constant phase and magnitude clock sources to the multiple die (i.e. multiple chiplets) in the package. Analysis is performed with multiple ARM CORTEX M0 cores per die of a homogeneous multi-die package architecture. Each M0 core of the multi-die package belongs to the unitary clock domain, designed with AI-ROA to operate at a frequency of 1 GHz. The multiple die are designed in the 28 nm technology node and the active interposer is designed in the 65 nm technology node. SP ICE based simulations of post-layout models provides analysis and evaluation of the proposed architecture for performance metrics under process, voltage, and temperature variations. In particular, performance metrics are reported for 1) power consumption in comparison to PLL based architectures designed and synthesized with an industrial tool, 2) robustness against process variations, and 3) clock skew across the cores throughout the multiple die.
Metrics
Details
- Title
- Robust Low Power Clock Synchronization for Multi-Die Systems
- Creators
- Ragh Kuttappa - Drexel UniversityBaris Taskin - Drexel UniversityScott Lerner - Drexel UniversityVasil Pano - Drexel UniversityIoannis Savidis - Drexel UniversityIEEE
- Publication Details
- 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), v 2019-, pp 1-6
- Series
- International Symposium on Low Power Electronics and Design
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000701430100047
- Scopus ID
- 2-s2.0-85072672193
- Other Identifier
- 991019170491904721
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- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Software Engineering
- Engineering, Electrical & Electronic