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SAT-attack Resilience Measure for Access Restricted Circuits
Conference proceeding

SAT-attack Resilience Measure for Access Restricted Circuits

Saran Phatharodom, Avesta Sasan and Ioannis Savidis
Proceedings of the 2021 on Great Lakes Symposium on VLSI
22 Jun 2021
DOI: https://doi.org/10.1145/3453688.3461759

Abstract

Class (computer programming) computer hardware & architecture Computer science electrical engineering, electronic engineering, information engineering Electronic circuit engineering and technology Hardware obfuscation Measure (mathematics) other engineering and technologies Resilience (network) restrict Scan chain strategic, defence & security studies Theoretical computer science Threat model
With the recent introduction of techniques to restrict scan chain access, a new class of deobfuscation problems emerge, in which the threat model, although similar to deobfuscation of a logic locked circuit, forms a novel class of attack. In this paper, the concept of a logic restricted circuit is generalized and defined. Next, a novel type of SAT-based attack is proposed for the new class of deobfuscation problems, described as a 2-stage SAT-attack. A SAT-attack resilience measure is developed to quantify the security strength of a logic restricted circuit against a SAT-based attack. Finally, the proposed SAT-resilience framework is applied to compare and evaluate effectiveness of example logic restriction schemes.

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