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Scalable Resonant Power Clock Generation for Adiabatic Logic Design
Conference proceeding

Scalable Resonant Power Clock Generation for Adiabatic Logic Design

Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin and IEEE Comp Soc
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 338-342
Jul 2021
DOI: https://doi.org/10.1109/ISVLSI51109.2021.00068

Abstract

Adiabatic Energy efficiency Logic gates RLC circuits Technological innovation Throughput Very large scale integration
In this paper, a scalable and passive component-less power-clock generation for adiabatic logic circuits, inclusive of the adiabatic core, is presented. The power-clock is traditionally a sinusoidal signal, that acts as the power and timing source to adiabatic gates. The slope of the power-clock signal directly impacts the overall energy efficiency of the adiabatic gates. Prior works have considered using LC based power-clock generation circuits, which are often considered costly due to area and high-Q inductor requirements. In this paper, a scalable solution is presented that features a unique innovation for the power clock generation circuit in step-charged circuits designed with resonant clocking. In particular, resonant rotary style clocking is used to provide the low power control to step-charged power clock circuits. SPICE based simulations are performed at 400 MHz on large scale adiabatic implementations of LGSynth'91 benchmark circuits. The overall energy efficiency of the proposed implementations are compared to those of equivalent adiabatic circuits with a traditional LC power-clock solution.

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Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
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