Conference proceeding
Simulation experiments of a high-performance RapidIO-based processing architecture
Proceedings IEEE International Symposium on Network Computing and Applications. NCA 2001, pp 336-339
2001
Abstract
Describes the results of our simulation analysis of a high-performance processing architecture based on the RapidIO network protocol. RapidIO is a 10-Gb/s, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. Two network topologies were simulated, a simple network consisting of an 8-port switch and eight processing nodes and a more extensive network consisting of five 8-port switches and 24 processing nodes. The results indicate that latencies as low as 92 ns for a remote 64-bit read request/response transaction may be achieved in an unloaded single-switch system. The effectiveness of various flow control mechanisms provided by the protocol are also explored, and when used in combination, a 10% increase in link utilization is achieved.
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Details
- Title
- Simulation experiments of a high-performance RapidIO-based processing architecture
- Creators
- J Adams - Rydal R&D Inc, PA, USAC KatsinisW RosenD HechtV AdamsH.V NarravulaS SukhtankarR LachenmaierIEEE COMPUTER SOCIETY
- Publication Details
- Proceedings IEEE International Symposium on Network Computing and Applications. NCA 2001, pp 336-339
- Conference
- IEEE International Symposium on Network Computing and Applications. NCA 2001
- Publisher
- IEEE
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Computer Science; Engineering Technology
- Web of Science ID
- WOS:000172335800041
- Scopus ID
- 2-s2.0-78650126569
- Other Identifier
- 991019173524704721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Information Systems
- Computer Science, Theory & Methods