Conference proceeding
Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design
2010 International Conference on Reconfigurable Computing and FPGAs, pp 400-405
Dec 2010
Abstract
This paper presents a custom hardware design for computing Singular Value Decomposition (SVD) of the radio communication channel characteristic matrix. The custom hard-ware was implemented to reduce the SVD computing time. The pipeline hardware developed is suitable for computing the SVD of a sequence of 2 × 2 complex-value matrices used in MIMO-OFDM standards, such as the IEEE 802.11n. The hardware developed achieves an optimum pipeline rate which equaled the maximum hardware clock rate. The proposed architecture provides performance gains over standard software libraries, such as the ZGESVD function of Linear Algebra Package (LAPACK) library, when running on standard processors.
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19 citations in Scopus
Details
- Title
- Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design
- Creators
- Yue Wang - Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USAK Cunningham - Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USAP Nagvajara - Drexel University, Electrical and Computer EngineeringJ Johnson - Comput. Sci., Drexel Univ., Philadelphia, PA, USA
- Publication Details
- 2010 International Conference on Reconfigurable Computing and FPGAs, pp 400-405
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering; Computer Science
- Scopus ID
- 2-s2.0-79951739805
- Other Identifier
- 991019173439604721