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Slew-down: analysis of slew relaxation for low-impact clock buffers
Conference proceeding

Slew-down: analysis of slew relaxation for low-impact clock buffers

Scott Lerner, Eric Leggett and Baris Taskin
2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), v 2017-
27 Jun 2017
DOI: https://doi.org/10.1109/SLIP.2017.7974910

Abstract

Algorithm design and analysis Benchmark testing Capacitance Clocks FinFETs Merging Timing
In the conventional ASIC design flow, slew constraints are imposed on clock sinks and clock buffers uniformly. The slew constraint has a significant affect not only on the timing but also on power in high performance designs. This paper investigates relaxing tight slew constraints for the reduction of low-impact buffers in clock trees. This is motivated by the observation that buffers in a clock tree that directly drive clock sinks have a high impact on meeting timing constraints. Buffers that drive other buffers in the clock tree do not directly impact the sink timing within some bound. These buffers can be considered low-impact, but still consume significant power. In order to reduce this power, the slew design constraint can be relaxed for low-impact buffers. Benchmarks from the ISPD2010 benchmark suite are synthesized to demonstrate the impact of a "slew-down" at the non-sink clock buffers of a clock tree with power and timing results from HSPICE. Results using a 20nm PTM FinFET technology at 4GHz shows that power savings of up to 50% (~10% on average) can be achieved compared to the minimum slew constraint while satisfying the same global slew constraint by a methodical slew-down process.

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