Conference proceeding
Slotted vias for dual damascene interconnects in 1 Gb DRAMs
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), pp 43-44
1999
Abstract
A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1 Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows us to combine low capacitance/high resistance lines with low resistance/high capacitance lines. The slotted vias are realized by a dual damascene integration scheme without adding an additional mask level or process cost, with excellent continuity yield and good electromigration performance.
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Details
- Title
- Slotted vias for dual damascene interconnects in 1 Gb DRAMs
- Creators
- R.F Schnabel - SiemensG BronnerL ClevengerD DobuzinskyG CostriniR FilippiJ GambinoM HugR IgguldenC LinK.P MullerG MuellerJ NuetzelC RadensS WeberF Zach
- Publication Details
- 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), pp 43-44
- Conference
- 1999 Symposium on VLSI Technology
- Publisher
- IEEE
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Other Identifier
- 991019203316804721