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Statistical Timing Analysis of Nonzero Clock Skew Circuits
Conference proceeding

Statistical Timing Analysis of Nonzero Clock Skew Circuits

Shannon Kurtas, Baris Taskin and IEEE
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, pp 605-608
01 Jan 2008
DOI: https://doi.org/10.1109/MWSCAS.2008.4616872

Abstract

Computer Science Computer Science, Hardware & Architecture Computer Science, Information Systems Engineering Engineering, Electrical & Electronic Science & Technology Technology
Statistical Static Timing Analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling (CSS) imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3 sigma variation), SSTA is observed to improve tire accuracy of measurement, thereby increasing the average clock period improvement to 38.25% as compared to zero clock skew circuits.

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1 citations in Web of Science
1 citations in Scopus

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Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Information Systems
Engineering, Electrical & Electronic
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