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SystemC model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation
Conference proceeding

SystemC model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation

C Tanougast, Y Berviller, C Mannino, H Rabah, M Janiaut and S Weber
Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004
2004
DOI: https://doi.org/10.1109/IWRSP.2004.1311111

Abstract

Bit rate Computer architecture Delay effects Digital video broadcasting Field programmable gate arrays Hardware Microelectronics Quality of service Software libraries Streaming media
The SystemC description language is used to model and simulate a digital hardware design in order to speed up its development. In this paper, we present the development of a real time bit-rate architecture for digital television data stream. The bit rate measurement of a digital program stream is one among other metrics of the quality of service (QoS) of a DVB transport Stream. This paper presents an electronic architecture tailored to the real time measurement of the bit rate of a MPEG2-DVB-T program. This architecture follows the standard published by the ETSI and has been modelled and validated by mean of the SystemC language. This model also allows to define implementation constraints and shows that the architecture can be entirely implemented in a FPGA with the help of a SystemC-VHDL translator.

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Computer Science, Hardware & Architecture
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