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Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis
Conference proceeding

Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis

Jianchao Lu, Xiaomi Mao, Baris Taskin and ACM/SIGDA
ISPD 11: PROCEEDINGS OF THE 2011 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, pp 131-138
01 Jan 2011
DOI: https://doi.org/10.1145/1960397.1960426

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

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4 citations in Web of Science
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Engineering, Electrical & Electronic
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