Conference proceeding
Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings
01 Jan 2022
Featured in Collection : UN Sustainable Development Goals @ Drexel
Abstract
Conference Title: 2022 IEEE International Symposium on Circuits and Systems (ISCAS) Conference Start Date: 2022, May 27 Conference End Date: 2022, June 1 Conference Location: Austin, TX, USAA transfer learning technique is proposed that utilizes models trained on data in one technology node to predict the performance of a circuit based on the sizing of transistors in another technology node. Specifically, neural networks optimally trained on data from the source technology node are adopted as pre-trained models. During transfer training, the front layers of the pre-trained models are frozen while the remaining layers are re-trained with significantly less data in the target technology node. The transfer learning technique is applied to the prediction of seven performance metrics of an operational amplifier based on seven design variables that include the sizing of transistors and capacitors. Models trained on a dataset containing 1602 simulated design points from a 180 nm process are transferred to predict the performance metrics of the op-amp utilizing only 100 simulated design points from a 65 nm process. During the training of the transferred models, the learning curve exhibits an improved starting point and a lower asymptotic error. Utilizing the same training set of 100 points from the 65 nm process, applying transfer learning reduces the normalized mean average error (MAE) on the test (inference) set in all cases by up to 50% as compared to training standalone models. For the transferred models, a detailed characterization of the test error as a function of the number of frozen layers is performed. Results indicate that the transferred gain predictor trained with only 100 data points provides a lower test error than the standalone model trained with 1000 data points without transfer learning in a 65 nm process. Therefore, transfer learning improves the sample efficiency of the training of the neural networks used for the prediction of the performance parameters of a circuit, which provides benefit for design migration when the collection of new circuit data is computationally costly in the target process node.
Metrics
Details
- Title
- Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes
- Creators
- Ioannis Savidis
- Publication Details
- The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings
- Publisher
- The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000946638601050
- Scopus ID
- 2-s2.0-85139236243
- Other Identifier
- 991019291687604721
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- Web of Science research areas
- Engineering, Electrical & Electronic