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VLSI architecture and FPGA implementation of a hybrid message-embedded self-synchronizing stream cipher
Conference proceeding

VLSI architecture and FPGA implementation of a hybrid message-embedded self-synchronizing stream cipher

C. Tanougast, S. Weber, G. Millerioux, J. Daafouz and A. Bouridane
DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, pp 386-389
01 Jan 2008
DOI: https://doi.org/10.1109/DELTA.2008.10

Abstract

Computer Science Computer Science, Information Systems Engineering Engineering, Electrical & Electronic Science & Technology Technology
In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions, subtractions, multiplications and word-switch operations. We show its feasibility and its implementation which are presented and detailed by using Altera FPGA technology for a set of parameter numbers (switching and key component number). We also show the parametrable of the HME in order to obtain the appropriate security and a the best trade off between the smallest FPGA logical area and the best throughputs rate for embedded applications.

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1 citations in Web of Science
5 citations in Scopus

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Domestic collaboration
International collaboration
Web of Science research areas
Computer Science, Information Systems
Engineering, Electrical & Electronic
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