Conference proceeding
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), v 2017-, pp 465-470
Jul 2017
Abstract
Wide wire sizes are often used in clock trees to improve timing characteristics and reduce electromigration effects. Recent research suggests the attractiveness of wide wires is affected by the forbidden pitch issues in the lithography of sub-20nm technologies. Parallel wiring is a recently proposed technique to get around these lithography issues in the routing stage of the ASIC design flow. Routing multiple minimum sized wires instead of wide wires is advantageous for i) improved metal density, and ii) is opportunistic, as the timing characteristics are dictated by the number of parallel wires. This paper proposes Wire Type clock tree synthesis, WT-CTS, the first CTS methodology to adapt parallel wiring types. WT-CTS utilizes the opportunity of changing timing characteristics through parallel wires to implement an incremental delay matching technique while the clock tree is being synthesized. A 20nm PTM technology is used in HSPICE simulation after ISCAS89 benchmarks are synthesized using WT-CTS. Results show up to a 92% reduction in skew and 12% power reduction while only increasing routing resources by 8% when compared to the minimum width design.
Metrics
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1 citations in Scopus
Details
- Title
- WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS
- Creators
- Scott Lerner - Drexel UniversityBaris Taskin - Drexel University
- Publication Details
- 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), v 2017-, pp 465-470
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Scopus ID
- 2-s2.0-85027278626
- Other Identifier
- 991019173730904721