Conference proceeding
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators
ispartofbook:IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)
2023
Abstract
Inter-chiplet communication is a fundamental bottleneck in scale-out Homogeneous Multi-Chip-Module-based Hardware Accelerators (HMCMHAs). This paper focuses on the problem of many-to-many communication traffic generated when dispatching output feature map tiles among chiplets. Such traffic has a strong impact on the latency and energy metrics of the HMCMHAs as it exposes the limitations of the existing wire-based Network-on-Package (NoP). This paper investigates augmenting the existing NoP with emerging wireless in-package communication links. The intrinsic single-hop and broadcastcapable technology is exploited to tackle the many-to-many communication traffic in question. We show that the proposed wireless-enabled NoP can significantly improve the latency and energy of Deep Neural Network (DNN) inference on HMCMHAs.
Metrics
Details
- Title
- Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators
- Creators
- M Palesi - University of CataniaE Russo - University of CataniaA Das - Université de RennesJ Jose - Indian Institute of Technology Guwahati
- Publication Details
- ispartofbook:IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:001055030700059
- Scopus ID
- 2-s2.0-85169298873
- Other Identifier
- 991021431020404721
InCites Highlights
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- Collaboration types
- Domestic collaboration
- International collaboration
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Interdisciplinary Applications
- Computer Science, Theory & Methods