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Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement
Conference proceeding

Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement

Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin and IEEE
2018 IEEE International Symposium on Circuits and Systems (ISCAS), v 2018-, pp 1-5
May 2018
DOI: https://doi.org/10.1109/ISCAS.2018.8351621

Abstract

Benchmark testing Degradation Heuristic algorithms Reliability Routing Runtime Topology
The emergence of Network-on-Chip (NoCs) as a scalable interconnection infrastructure for Chip Multi-Processors (CMPs) creates the need to analyze the degradation and lifetime repercussions incurred by network traffic from exa-scale and distributed workloads. Reliability methods and redundancies are in place to circumvent defective parts or to roll back to a previous safe state. These reliability techniques are reactive in nature and do not focus effort in avoiding degradation which may result in full system failure. Current methods for improving degradation and lifetime focus on design and runtime optimizations. This paper proposes a workload-aware routing algorithm, which complements known techniques and optimizes the overall network traffic balance. The end product is a methodology that utilizes workload signatures and priority-based routing to improve port and router utilization across the network. The proposed WAR algorithm stays within ≈2% of the latency and average hop count of a NoC using XY routing. Simulation results show an improvement in network traffic balance upto ≈17% (average improvement of ≈8.6%) with WAR on NoCs for lifetime improvement.

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3 citations in Web of Science
10 citations in Scopus

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Web of Science research areas
Engineering, Electrical & Electronic
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