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A field-programmable and secure array for prototyping analog circuits
Dissertation   Open access

A field-programmable and secure array for prototyping analog circuits

Ziyi Chen
Doctor of Philosophy (Ph.D.), Drexel University
Jun 2026
DOI:
https://doi.org/10.17918/00011504
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Abstract

Field-programmable analog arrays Hardware security Reconfigurability Synthesis algorithms
The focus of this dissertation is the development of a field-programmable and secure analog array. The research presented in this dissertation advances programmable analog hardware in architecture, security, and synthesis, and establishes a foundation for rapid prototyping, circuit mapping, secure implementation, and automated configuration of analog and mixed-signal systems. The developed field-programmable analog array (FPAA) is comprised of a 3 x 4 configurable analog block (CAB) array, with a single configurable logic block (CLB) added to each column to allow for the programming of digital circuits. Passive devices, including programmable capacitors and resistors, and active transistor pairs, are utilized to implement both continuous-time and discrete-time circuits. The implemented first-order delta-sigma modulator operates at a frequency of 15 MHz and provides an effective number of bits (ENOB) of 6.8 when utilizing an oversampling ratio of 128x. The configured pipeline ADC provides an ENOB of 3.76 for a sampling frequency of 15 MHz. A placement and mapping algorithm is developed to efficiently assign analog circuits onto the FPAA fabric while compensating for the degradation in performance introduced by the parasitic impedance of the routing switches. The shift in the DC operating voltage and any performance degradation due to the ON-resistance of the routing switches is addressed by re-sizing the width of the transistors after vertical and horizontal mapping. Routers are provided in the fabric to connect devices implemented on the FPAA while minimizing the resistance along the current path. The developed FPAA is also utilized to secure against hardware threats that include IP piracy and counterfeiting. A hybrid architecture that combines an application specific integrated circuit (ASIC) and an FPAA (ASIC-FPAA) is developed to address the performance security trade-off in analog circuits. A programmable transistor pair (TP) is developed that obfuscates the topology of an analog circuit within an array of transistor pairs while minimizing the degradation in circuit performance due to the implemented security features. A method to obfuscate the entire topology of an analog circuit is also developed. The FPAA provides the highest-level of security robustness as the entire circuit topology is programmed onto the array of the fabric, while trading-off performance. For the delta-sigma ([delta][sigma]) modulator, the comparator module is selected for implementation on the FPAA fabric, which results in a reduction of less than 0.25% in the effective number of bits (ENOB) and an increase of 8.6% in the power consumption as compared to an unobfuscated [delta][sigma] modulator. A metric that evaluates the topology complexity after obfuscation is also developed. Results indicate that the developed techniques provide a 5x improvement in security as measured by a developed metric without compromising performance. In addition, a framework is developed to automatically generate circuit topologies on an FPAA based on user-provided specifications. A Monte Carlo Tree Search (MCTS) algorithm is utilized to optimize device selection, transistor pair topology selection, and routing. A group search (GS) algorithm is developed to increase the efficiency of the MCTS algorithm during device selection and routing selection. For the generated op amps, a gain of 31.11 dB, a 3-dB bandwidth of 15.85 MHz, and a phase margin of 46.31 degrees is achieved when the maximum allowed iterations of MCTS algorithm is set to 130. Compared with random tree search, the developed utilization of the MCTS algorithm with group search achieves a 56% higher score for a figure of merit (FOM) that accounts for gain, 3-dB bandwidth, unity-gain frequency (UGF), phase margin, common-mode rejection ratio (CMRR), and slew rate after 15 iterations of tree search for the synthesis of op amps. In summary, the work described in this dissertation enhances FPAA technology by advancing programmable implementation, circuit mapping, hardware security, and topology synthesis for analog and mixed-signal circuits.

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