Bounded and variation-aware design for clock tree synthesis

Scott Philip Lerner

doi:10.17918/00010654

As semiconductor technology continues to advance at an unprecedented pace, the integration of smaller and more densely packed transistors on silicon wafers has ushered in an era of unrivaled power and energy efficiency. However, this rapid advancement also introduces a significant and growing challenge: the increasing problem of process variation. Variations in manufacturing processes, device characteristics, and environmental conditions can result in large changes to performance and reliability for integrated circuits (IC). These variations introduce substantial hurdles to achieving predictable timing performance in modern electronic systems. This work delves into the multifaceted issue of process variation and presents a novel, variation-aware clock tree synthesis methodology (Var-CTS) to address that variation. Var-CTS is used during the initial synthesis stage of physical design to improve the statistical worst case timing. Using a timing library characterized for variation, the methodology uses variation-aware merging regions for skew that improve timing and resilience against variation. Building up to the variation-aware clock tree synthesis, two studies for clock slew and wiring type are performed and one methodology considering bounded clock tree synthesis is presented. The first study explores the effects of slew on clock power and timing. The study shows that slew constraint manipulation can improve power consumption while maintaining high-performance operation. A study of a uniquely fundamental wiring type is performed that can improve routing density, an important aspect for reducing wire variations during manufacturing. The implemented wiring type is determined to have positive effects on both the timing of the implemented clock trees with the added consideration of routing density. A bounded skew and slew merging region methodology for clock tree synthesis is presented to improve performance of the implemented clock tree. The methodology shows improvement over previous research due to multi-constraint merging regions during the clock tree synthesis merging process. Finally, the variation-aware clock tree synthesis methodology is presented. Results from Monte Carlo-based simulations show how including statistical timing information in the clock tree synthesis methodology improves the final statistical worst-case skew variation of a high-performance clock tree.

Bounded and variation-aware design for clock tree synthesis

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Bounded and variation-aware design for clock tree synthesis

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