There exist Fast Fourier transform (FFT) algorithms, called dimensionless FFTs1, that work independent of dimension. These algorithms can be configured to compute different dimensional discrete Fourier transforms (DFTs) simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows the design of a universal FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this thesis a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow is designed. Mathematical properties of the FFT are used systematically to simplify and optimize the processor design, and to explore different algorithms and design choices. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. A performance model is used to evaluate the different algorithmic choices and their resulting dataflow. Using the performance model, a search was conducted to find the optimal algorithm for the family of processors considered. The resulting algorithm and corresponding hardware design was implemented using FPGA. 1L. Auslander, J. Johnson and R. Johnson, Dimensionless Fast Fourier Transform Method and Apparatus, Patent #US5003056, issued Dec. 14, 1999.
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Details
Title
Design, optimization, and implementation of a universal FFT processor
Creators
Pinit Kumhom
Contributors
Jeremy Russell Johnson (Advisor) - Drexel University, Drexel University (1970-)
Prawat Nagvajara (Advisor) - Drexel University, Drexel University (1970-)
Awarding Institution
Drexel University
Degree Awarded
Doctor of Philosophy (Ph.D.)
Publisher
Drexel University; Philadelphia, Pennsylvania
Number of pages
xx, 268 pages
Resource Type
Dissertation
Language
English
Academic Unit
College of Arts and Sciences; Mathematics and Computer Science [Historical]; Drexel University
Other Identifier
991021888884204721
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