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Enhancing the cybersecurity root of trust through hardware layer logic obfuscation
Dissertation   Open access

Enhancing the cybersecurity root of trust through hardware layer logic obfuscation

Kyle Juretus
Doctor of Philosophy (Ph.D.), Drexel University
Sep 2020
DOI:
https://doi.org/10.17918/00000159
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Abstract

Integrated circuits--Design and construction Data encryption (Computer science) Computers--Circuits--Design and construction Computer software--Development Web applications--Programming Computer Security
While the security of software has garnered significant attention in the cybersecurity landscape, the expanding utilization of untrusted third parties within the hardware supply chain raises concern over the security of the hardware layer. This dissertation focuses on 1) developing low-cost logic locking solutions, 2) incorporating logic locking into the electronic design automation (EDA) flow, and 3) enhancing the security of logic locking against oracle guided attacks. When an oracle guided attack is not part of the threat space, the main constraint limiting the application of in-cone logic locking techniques is the overhead in area, power, and performance needed to add the locking elements to the circuit. Gate level logic locking techniques are presented that reduce the overhead of logic locking, which results in a 34.54% increase in performance, 41.50% reduction in power, and a 43.58% reduction in area as compared to XOR-based logic locking methodologies. When oracle guided attacks are considered as part of the threat model, the security of in-cone logic locking techniques is significantly reduced. The security of in-cone logic locking against oracle guided attacks is, therefore, characterized. The analysis is then utilized to develop three gate selection algorithms that result in an increase of the average number of iterations to complete an oracle guided attack by 61.8% when securing 5% of the logic gates of a netlist. The results demonstrate that while the security of in-cone logic locking techniques is improved, oracle guided attacks still prove effective due to the logical masking of key gates within the circuit. To increase the security against oracle guided attacks, a sequential logic locking methodology utilizing hidden state transitions is developed. By reducing the information leakage of the structure of the circuit added to secure the IC, the key space for an adversary to search greatly increases. The larger search space results in an increase in the average expected time to determine the key from 48 hours to 1.64 x 10^12 years for the ISCAS'89 s15850 benchmark circuit. A methodology to increase the output corruption of out-of-cone logic locking techniques while maintaining a high level of security against oracle guided attacks is also developed. The methodology results in an increase in the number of iterations required to complete a SAT attack for a 20 input circuit implementing a flip function by 34.41x over SFLL-HD n/4 and 82.36x over SFLL-Flex. Overall, the methodologies presented in this dissertation increase the security of logic locking while limiting the impact on power, performance, area, and design time. The presented work, therefore, allows for the addition of security as a design constraint, which provides a more secure cybersecurity landscape.

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