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Generating efficient hardware from high-level functional languages
Dissertation   Open access

Generating efficient hardware from high-level functional languages

Mahshid Shahmohammadian
Doctor of Philosophy (Ph.D.), Drexel University
Sep 2021
DOI:
https://doi.org/10.17918/00000895
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Abstract

Very High-Speed Integrated Circuit (VHSIC) hardware description language (VHDL) and Verilog are the two commonly used HDLs in circuit design. In these verbose languages, the hardware designer must often rewrite repetitive code patterns only because the language does not allow for creating new abstractions to eliminate boilerplate code-a piece of code that can be reused several times. VHDL and Verilog enable very limited abstractions for the designer such as the abstraction over bit-width of input/output. New abstractions allow the programmers to focus on high-level specifications and the core computations rather than low-level tedious programming. Leveraging functional language tools allow the designers to build new abstractions and, most importantly, enable modularity and compositionality. As circuits become larger, factoring out common code into new abstractions makes it easier to modify and extend the design. The ability to build new abstractions to reduce programming effort should not, however, come at the cost of performance in hardware design. This thesis first investigates the performance characteristics of high-level functional hardware designs by utilizing Kansas Lava (Gill et al., 2009), a commonly used functional HDL (FHDL), across a number of experimental studies. This includes re-implementations of a Simulink model of orthogonal frequency-division multiplexing (OFDM) (Chacko et al., 2014) components and Intellectual Property (IP) core developments for several Xilinx IPs. Despite demonstrating promising performance and resource utilization when evaluated as individual combinational blocks, we observed performance shortcomings associated with the handshaking of pipeline stages in Kansas Lava FHDL implementations. To eliminate the performance cost, this thesis introduces a VHDL metaprogramming technique, called metaprogramming with combinators, that leverages Haskell as a sophisticated "macro language" to provide designers with new tools and abstractions for expressing circuits without sacrificing control or performance. We generate VHDL by directly embedding VHDL syntax in Haskell by taking advantage of the quasiquotation feature in Haskell. Using quasiquotation, the programmer can directly manipulate the concrete syntax of VHDL for fine control over the generated VHDL while specifying the circuit at a high level. Metaprogramming with combinators allows expressing new tools and abstractions as libraries without changing the language or compiler. A high-level combinator library for specifying hardware pipelines and a library for designing combinational circuits are among the useful available libraries. Finally, using the aforementioned libraries, several IP cores are implemented and show competent performance with corresponding Xilinx IPs. The high-level pipeline library presented in this thesis consists of a standard valid/ready handshaking protocol for the circuits. However, other pipeline protocols can be added to the library without changing the circuit specification. Therefore, designers can both write new abstractions, and use (or extend) the available tools using this technique while still having full control over the performance.

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