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Reimagining the role of network-on-chip resources toward improving chip multiprocessor performance
Dissertation   Open access

Reimagining the role of network-on-chip resources toward improving chip multiprocessor performance

Karthik Sangaiah
Doctor of Philosophy (Ph.D.), Drexel University
Dec 2020
DOI:
https://doi.org/10.17918/00000254
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Sangaiah_Karthik_20209.39 MBDownloadView

Abstract

Electrical engineering Computer networks--Data processing Networks on a chip Computer simulation Computer Architecture
The design of on-chip communication networks is paramount to sustaining and improving the computation throughput of many-core chip multiprocessors (CMP). As advances in packaging technologies, such as multi-die systems (MDS), have enabled scaling up of CMPs to host hundreds of CPU cores within a package, Network-on-Chips (NoC) are critical for scalably moving data between cores and memory. However, as a growing component in many-core CMPs, scrutiny needs to be applied on how NoCs are modeled, how tradeoffs are made with the rest of the CMP uncore, and how NoC provisioning can impact system performance. Using the tools and design space exploration methodologies detailed in this dissertation, contemporary NoCs are found to frequently experience long periods of idle time, with less than 10% network link and router utilization in High Performance Computing (HPC) applications. The combination of this design slack and the available resources of modern packaging technologies present opportunities to have a fundamental shift in the utility of network routers, toward NoCs embedded with computation functionality.

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