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Scalable and shareable resonant rotary clocks
Dissertation   Open access

Scalable and shareable resonant rotary clocks

Ragh Kuttappa
Doctor of Philosophy (Ph.D.), Drexel University
Dec 2021
DOI:
https://doi.org/10.17918/00000675
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Abstract

Integrated circuits--Large scale integration--Design and construction--Automation Heterogeneous computing Application-specific integrated circuits Voltage regulators
Modern integrated circuits are becoming more heterogeneous both in terms of technology and architecture. With the increase in number of cores and design complexity, there is an increasing need for energy efficient hardware solutions. Along with the increasing complexity of the architecture, the power consumption of the clock distribution network in integrated circuits is continuously increasing. Resonant clocking has been studied as an alternative solution to conventional clock distribution networks. Resonant rotary clocks is a type of resonant clocking which works on the adiabatic switching principles, providing complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous architectures. In this dissertation, an ASIC compliant resonant rotary clocking synthesis methodology is developed to integrate novel algorithms and low-power solutions to enable: 1) scalable, and 2) shareable resonant clocking architecture. Resonant rotary clocks are designed to provide a low-power unitary clock domain solution across an individual die and multiple dies. The resonant rotary clocks are used to provide robust clock signals for high-speed interface circuits across a package. In addition, the resonant rotary clocks are used to provide multiphase clock signals to on-chip voltage regulators. The proposed solutions are compared to conventional clock distribution designs designed with phase locked loops (PLL) to demonstrate power savings, reliability, and area savings.

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