A low latency switch architecture for high-performance packet-switched networks

Thesis

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Satyen A. Sukhtankar

Master of Science (M.S.), Drexel University

2003

DOI:

https://doi.org/10.17918/00008895

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Electrical engineering

Packet switching (Data transmission)

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Title: A low latency switch architecture for high-performance packet-switched networks
Creators: Satyen A. Sukhtankar
Contributors: Warren A. Rosen (Advisor) - Drexel University, Drexel University (1970-)
Awarding Institution: Drexel University
Degree Awarded: Master of Science (M.S.)
Publisher: Drexel University; Philadelphia, Pennsylvania
Number of pages: xi, 101 pages
Resource Type: Thesis
Language: English
Academic Unit: College of Engineering (1970-2026); Electrical (and Computer) Engineering [Historical]; Drexel University
Other Identifier: 991021888978104721