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High level synthesis implementation of real-time video stabilization
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High level synthesis implementation of real-time video stabilization

Alexander Noce
Master of Science (M.S.), Drexel University
Jun 2020
DOI:
https://doi.org/10.17918/00000069
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Abstract

Field programmable gate arrays Self-stabilization (Computer science) Systems Engineering
In this paper, an implementation of real-time video stabilization is presented utilizing a high-level synthesis (HLS) workflow, in which high-level, abstracted code is translated into hardware defining register transfer level code. The implementation is written in C++ in the Vivado HLS environment targeting the Xilinx Ultrascale+ MPSoC (Multi-Processor System on Chip) ZCU102 development board. The stabilizer is designed such that it can operate in real-time; the frame processing start interval is shorter than the frame rate of the video stream. The stabilization process begins with a feature detection and description algorithm called ORB, Oriented Fast and Rotated BRIEF, a combination of the Features from Accelerated Segment Test (FAST) detector and Binary Robust Independent Features (BRIEF) descriptor. Features are then matched using the Hamming distance, and a translational motion vector is generated using an alpha-beta filter. The video is then stabilized using the filtered motion vector. The interframe transformation fidelity measure is used to quantify the performance of the stabilization. The video stabilization core can process in real-time up to 1920x1080@60fps and utilizes less than 3% of the logic resources and around 10% of the block RAM resources within the FPGA.

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