A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

Journal article

Peer reviewed

Jianchao Lu, Ying Teng and Baris Taskin

IEEE transactions on very large scale integration (VLSI) systems, Vol.20(6), pp.1002-1011

Jun 2012

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Title: A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
Creators: Jianchao Lu
Ying Teng
Baris Taskin
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, Vol.20(6), pp.1002-1011
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Resource Type: Journal article
Language: English
Academic Unit: Electrical and Computer Engineering
Identifiers: 991014878018504721

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Web of Science research areas: Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic