Logo image
A new ADPLL architecture dedicated to program clock references synchronization
Journal article   Peer reviewed

A new ADPLL architecture dedicated to program clock references synchronization

C. Mannino, H. Rabah, S. Weber, C. Tanougast, Y. Berviller and M. Janiaut
International journal of electronics, v 93(12), pp 843-861
01 Dec 2006

Abstract

All digital phase locked loop DVB-T Frequency synthesizer Jitter Program clock reference
This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.

Metrics

10 Record Views
7 citations in Scopus

Details

InCites Highlights

Data related to this publication, from InCites Benchmarking & Analytics tool:

Web of Science research areas
Engineering, Electrical & Electronic
Logo image