Journal article
A shift-register-based QCA memory architecture
ACM journal on emerging technologies in computing systems, v 5(1), pp 1-18
Jan 2009
Abstract
A quantum-dot cellular automata (QCA) design of an nxm -bit, shift-register-based memory architecture is presented. The architecture maintains data at a stable conformation, which is contrary to traditional data in-motion concept for QCA architectures. The memory architecture is based on an existing dual-phase-synchronized, line-based, one-bit QCA memory cell building block that provides size and latency improvements over other known one-bit memory cells through its novel clocking scheme. Read/write latencies up to ∼2X lower than the existing tile-based architecture with three-phase, line-based memory cells are obtained. Simulations with QCADesigner and HDLQ are performed on a sample 4 x 8 bit memory architecture implementation.
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Details
- Title
- A shift-register-based QCA memory architecture
- Creators
- Baris Taskin - Drexel University, Philadelphia, PAAndy Chiu - Drexel University, Philadelphia, PAJonathan Salkind - Drexel University, Philadelphia, PADaniel Venutolo - Drexel University, Philadelphia, PA
- Publication Details
- ACM journal on emerging technologies in computing systems, v 5(1), pp 1-18
- Publisher
- Association for Computing Machinery
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000265879100004
- Scopus ID
- 2-s2.0-60349121974
- Other Identifier
- 991014878059704721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic
- Nanoscience & Nanotechnology