Journal article
Adaptive ADPLL architecture for MPEG system clock related measurements in variable rate environment
Sensors and actuators. A. Physical, v 147(2), pp 633-640
03 Oct 2008
Abstract
Measurements such as jitter, frequency offset and drift are very important in the quality of service evaluation in digital video broadcast, especially under varying rate environment. This paper presents anal I digital phase locked loop (ADPLL) architecture for either VLSI or low cost FPGA implementation. The operation of proposed ADPLL is based on a frequency synthesizer for a very narrow band frequency (+/- 800 Hz), small frequency step and high central frequency (27 MHz). The proposed solution is designed for the real time measurements, feature a very low intrinsic jitter, and adaptive rate variation. The system description and adaptation method are presented with corresponding hardware implementation. Experimental results in term of jitter analysis and adaptation behavior are detailed and discussed. (c) 2008 Elsevier B.V. All rights reserved.
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Details
- Title
- Adaptive ADPLL architecture for MPEG system clock related measurements in variable rate environment
- Creators
- H. Rabah - Nancy-UniversitéC. Mannino - Nancy-UniversitéY. Berviller - Nancy-UniversitéC. Tanougast - Nancy-UniversitéS. Weber - Nancy-Université
- Publication Details
- Sensors and actuators. A. Physical, v 147(2), pp 633-640
- Publisher
- Elsevier
- Number of pages
- 8
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000259685600040
- Scopus ID
- 2-s2.0-49649123248
- Other Identifier
- 991019203697604721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Engineering, Electrical & Electronic
- Instruments & Instrumentation