Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Reducing power consumption requires the development of system-on-chip implementations that must provide both energy efficiency and adequate performance to meet the demands of the long deployment lifetimes and bursts of computation that characterize wireless sensor network (WSN) applications. Therefore, this work argues that designers should evaluate the design in terms of average power for an entire workload, including active and idle periods, not just the metric of energy-per-instruction.
The proposed architecture fully embraces the accelerator-based computing paradigm, including acceleration for the network layer ( routing) and application layer (data filtering). Moreover, the architecture can disable the accelerators via VDD-gating to minimize leakage current during the long idle times common to WSN applications. We have implemented the system architecture in 130 nm CMOS which has been tested to operate at 550 mV and 12.5 MHz. Our system uses 100 less power when idle than a traditional microcontroller, and 10-600 less energy when active. This work concludes with an analysis across a wide range of workloads that shows how the system provides energy efficient operation for both low, medium, and high intensity workloads.