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Clock Distribution Networks in 3-D Integrated Systems
Journal article   Open access   Peer reviewed

Clock Distribution Networks in 3-D Integrated Systems

Vasilis F. Pavlidis, Ioannis Savidis and Eby G. Friedman
IEEE transactions on very large scale integration (VLSI) systems, v 19(12), pp 2256-2266
01 Dec 2011
url
https://doi.org/10.1109/tvlsi.2010.2073724View
Published, Version of Record (VoR)Open Access (License Unspecified) Open

Abstract

Computer Science Computer Science, Hardware & Architecture Engineering Engineering, Electrical & Electronic Science & Technology Technology
3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.

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Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
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