3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.
Clock Distribution Networks in 3-D Integrated Systems
Creators
Vasilis F. Pavlidis - École Polytechnique Fédérale de Lausanne
Ioannis Savidis - University of Rochester
Eby G. Friedman - University of Rochester
Publication Details
IEEE transactions on very large scale integration (VLSI) systems, v 19(12), pp 2256-2266
Publisher
IEEE
Number of pages
11
Grant note
Intel Corporation
New York State Office of Science, Technology & Academic Research
Eastman Kodak Company
Freescale Semiconductor Corporation
CCF-0541206; CCF-0811317; CCF-0829915 / National Science Foundation; National Science Foundation (NSF)
Resource Type
Journal article
Language
English
Academic Unit
Electrical and Computer Engineering
Web of Science ID
WOS:000296459300011
Scopus ID
2-s2.0-80455158008
Other Identifier
991019186791004721
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