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Delay insertion method in clock skew scheduling
Journal article   Peer reviewed

Delay insertion method in clock skew scheduling

B Taskin and I.S Kourtev
IEEE transactions on computer-aided design of integrated circuits and systems, v 25(4), pp 651-663
Apr 2006
DOI: https://doi.org/10.1109/TCAD.2006.870072

Abstract

Job shop scheduling Uncertainty Circuit optimization digital synchronous very large scale integration (VLSI) circuit timing Very large scale integration Circuit analysis Delay Delay padding nonzero clock skew scheduling Frequency Timing reconvergent paths Signal design Clocks
This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement of circuit performance achievable through clock skew scheduling. A delay insertion method is proposed such that the optimal clock period achievable through clock skew scheduling is improved by mitigating the limitations caused by reconvergent paths. Experimental results demonstrate that reconvergent paths are limiting for 34% (41% for level sensitive) of the selected suite of ISCAS'89 benchmark circuits. Through the application of clock skew scheduling with delay insertion, an average improvement of 10% shorter clock periods (9% for level sensitive) is observed for ISCAS'89 benchmark circuits compared to the results of conventional clock skew scheduling.

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18 citations in Web of Science
23 citations in Scopus

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Collaboration types
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Interdisciplinary Applications
Engineering, Electrical & Electronic
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