Journal article
Design, optimization, and implementation of a universal FFT processor
Proceedings - IEEE International ASIC Conference and Exhibit
01 Jan 2000
Abstract
There exist Fast Fourier transform (FFT) algorithms, called dimensionless FFTs, that work independent of dimension. These algorithms can be configured to compute different dimensional DFTs simply by relabeling the input data and by changing the values of the twiddle factors occurring in the butterfly operations. This observation allows us to design an FFT processor, which with minor reconfiguring, can compute one, two, and three dimensional DFTs. In this paper we design a family of FFT processors, parameterized by the number of points, the dimension, the number of processors, and the internal dataflow, and show how to map different dimensionless FFTs onto this hardware design. Different dimensionless FFTs have different dataflows and consequently lead to different performance characteristics. Using a performance model we search for the optimal algorithm for the family of processors we considered. The resulting algorithm and corresponding hardware design was implemented using FPGA.
Metrics
Details
- Title
- Design, optimization, and implementation of a universal FFT processor
- Creators
- Pinit Kumhom - Drexel UniversityJeremy JohnsonPrawat Nagvajara
- Publication Details
- Proceedings - IEEE International ASIC Conference and Exhibit
- Publisher
- The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering; Computer Science
- Web of Science ID
- WOS:000165305200035
- Scopus ID
- 2-s2.0-0033713342
- Other Identifier
- 991019168911204721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic