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Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits
Journal article   Peer reviewed

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits

Ioannis Savidis, Boris Vaisband and Eby G Friedman
IEEE transactions on very large scale integration (VLSI) systems, v 23(10), pp 2077-2089
Oct 2015

Abstract

3-D heat transfer 3-D integrated circuit (IC) 3-D thermal effects Heating Metals Temperature measurement Temperature sensors thermal propagation Thermal resistance
A 3-D test circuit examining thermal propagation within a through-silicon via-based 3-D integrated stack has been designed, fabricated, and tested. Design insight into thermal coupling in 3-D integrated circuits (ICs) through both experiment and simulation is provided, and suggestions to mitigate thermal effects in 3-D ICs are offered. Two wafers are vertically bonded to form a 3-D stack. Intraplane and interplane thermal coupling is investigated through single-point heat generation using resistive thermal heaters and temperature monitoring through four-point resistive measurements. Thermal paths are identified and analyzed based on the metric of thermal resistance per unit length. The peak steady-state temperature due to die location within a 3-D stack is described. The reduction in peak temperature through fan-based active cooling is also reported. Thermal propagation from a heat source located on the backside of the silicon is examined with both back metal and on-chip thermal sensors. A comparison of thermal coupling between two different heat sources on the same device plane is also provided.

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Collaboration types
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
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