Journal article
FOPAC: Flexible On-Chip Power and Clock
IEEE transactions on circuits and systems. I, Regular papers, v 66(12), pp 4628-4636
Dec 2019
Abstract
A novel flexible on-chip power and clock (FOPAC) generation and distribution circuit is proposed to enable fast dynamic voltage and frequency scaling (DVFS). FOPAC utilizes resonant rotary clocks (ReRoCs) along with multi-phase voltage regulators (MPVR) for the clock and power generation and distribution. The locally distributed ReRoCs provide the required clock phases to the MPVR, and the MPVR provides the required voltage levels to the ReRoC, providing spatial and temporal flexibility for fast DVFS. The ReRoC and MPVR share the on-chip fly capacitor of the switched capacitor voltage regulators to achieve greater frequency scaling at run-time while reducing the overhead. The FOPAC architecture is evaluated on industrial designs demonstrating a <; 2 ns DVFS switching time.
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Details
- Title
- FOPAC: Flexible On-Chip Power and Clock
- Creators
- Ragh Kuttappa - Drexel UniversitySelcuk Kose - University of RochesterBaris Taskin - Drexel University
- Publication Details
- IEEE transactions on circuits and systems. I, Regular papers, v 66(12), pp 4628-4636
- Publisher
- IEEE
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000502344800008
- Scopus ID
- 2-s2.0-85076372088
- Other Identifier
- 991019168055904721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Collaboration types
- Domestic collaboration
- Web of Science research areas
- Engineering, Electrical & Electronic