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FinFET-Based Low-Swing Clocking
Journal article   Peer reviewed

FinFET-Based Low-Swing Clocking

Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin
ACM journal on emerging technologies in computing systems, v 12(2)
01 Aug 2015

Abstract

Computer Science Computer Science, Hardware & Architecture Engineering Engineering, Electrical & Electronic Nanoscience & Nanotechnology Science & Technology Science & Technology - Other Topics Technology
A low-swing clocking methodology is introduced to achieve low-power operation at 20nm FinFET technology. Low-swing clock trees are used in existing methodologies in order to decrease the dynamic power consumption in a trade-off for 3 issues: (1) the effect of leakage power consumption, which is becoming more dominant when the process scales sub-32nm; (2) the increase in insertion delay, resulting in a high clock skew; and (3) the difficulty in driving the existing DFF sinks with a low-swing clock signal without a timing violation. In this article, a FinFET-based low-swing clocking methodology is introduced to preserve the dynamic power savings of low-swing clocking while minimizing these three negative effects, facilitated through an efficient use of FinFET technology. At scaled performance constraints, the proposed methodology at 20nm FinFET leads to 42% total power savings (clock network+DFF) compared to a FinFET-based full-swing counterpart at the same frequency (3 GHz), thanks to the dynamic power savings of low-swing clocking and 3% power savings compared to a CMOS-based low-swing implementation running at the half frequency (1.5 GHz), thanks to the leakage power savings of FinFET technology.

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14 citations in Scopus

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Domestic collaboration
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Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Nanoscience & Nanotechnology
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