Journal article
Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
IEEE transactions on very large scale integration (VLSI) systems, v 16(12), pp 1648-1656
Dec 2008
Abstract
This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the QCADesigner simulator are performed to verify the functionality of the proposed QCA memory cell.
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Details
- Title
- Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
- Creators
- B Taskin - Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PABo Bo Hong - Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, v 16(12), pp 1648-1656
- Publisher
- IEEE
- Resource Type
- Journal article
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000261447900007
- Scopus ID
- 2-s2.0-56749133331
- Other Identifier
- 991014878309404721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic