Logo image
Back
Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators
Journal article   Open access   Peer reviewed

Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators

Md Shazzad Hossain and Ioannis Savidis
IEEE journal on emerging and selected topics in circuits and systems, v 11(4), pp 762-775
Dec 2021
DOI: https://doi.org/10.1109/JETCAS.2021.3121687
Featured in Collection :   UN Sustainable Development Goals @ Drexel
url
https://doi.org/10.1109/jetcas.2021.3121687View
Accepted (AM)Open Access (Publisher-Specific),  Open

Abstract

Computational modeling Computer architecture edge devices heterogeneous DNN accelerator Leakage currents Leakage reuse Memory management near-memory computing on-chip SRAM Random access memory Receivers System-on-chip ubiquitous DNN applications
The exploration of custom deep neural network (DNN) accelerators for highly energy constrained edge devices with on-device intelligence is gaining traction in the research community. Despite the superior throughput and performance of custom accelerators as compared to CPUs or GPUs, the energy efficiency and versatility of state-of-the-art DNN accelerators is constrained due to a) the storage and movement of a large volume of data and b) the limited scope of monolithic architectures, where the entire accelerator executes only a single model at any given time. In this paper, a multi-voltage domain heterogeneous DNN accelerator is proposed that executes multiple models simultaneously with different power-performance operating points. The proposed architecture concurrently implements near-memory computing and leakage reuse, where the leakage current of idle memory banks within each processing element is utilized to deliver current to the adjacently placed multiply-and-accumulate (MAC) units. The proposed architecture and circuit techniques are evaluated with SPICE simulation in a 65 nm CMOS technology. The simulation results indicate that the proposed heterogeneous architecture with leakage reuse results in an energy efficiency of 3.27 tera-operations per second per watt (TOPS/W) as compared to a conventional monolithic and single voltage domain architecture that exhibits an energy efficiency of 0.0458 TOPS/W. In addition, the proposed accelerator that implements the leakage reuse technique on only half of the memory elements storing the weights reduces the power consumption of the sub-arrays of processing elements by 26% (99.4 mW) as compared to an accelerator that does not apply leakage reuse.

Metrics

19 Record Views
2 citations in Web of Science
2 citations in Scopus

Details

UN Sustainable Development Goals (SDGs)

This publication has contributed to the advancement of the following goals:

#3 Good Health and Well-Being

InCites Highlights

Data related to this publication, from InCites Benchmarking & Analytics tool:

Web of Science research areas
Engineering, Electrical & Electronic
Logo image