Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Journal article

Peer reviewed

Baris TASKIN and Ivan S KOURTEV

IEEE transactions on very large scale integration (VLSI) systems, v 12(1), pp 12-27

2004

Additional Links

Integrated circuits

Electronics

Applied sciences

Integrated circuits by function (including memories and processors)

Exact sciences and technology

Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices

7 Record Views

10 citations in Scopus

Title: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
Creators: Baris TASKIN - Department of Electrical Engineering, School of Engineering, University of Pittsburgh, Pittsburgh, PA 15261, United States
Ivan S KOURTEV - Department of Electrical Engineering, School of Engineering, University of Pittsburgh, Pittsburgh, PA 15261, United States
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, v 12(1), pp 12-27
Publisher: Institute of Electrical and Electronics Engineers; Piscataway, NJ
Resource Type: Journal article
Language: English
Academic Unit: Electrical and Computer Engineering
Web of Science ID: WOS:000188735900001
Scopus ID: 2-s2.0-1342286837
Other Identifier: 991014877750404721

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Web of Science research areas: Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic