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MODELS OF DISTRIBUTED-SHARED-MEMORY ON AN INTERCONNECTION NETWORK FOR BROADCAST COMMUNICATION
Journal article   Peer reviewed

MODELS OF DISTRIBUTED-SHARED-MEMORY ON AN INTERCONNECTION NETWORK FOR BROADCAST COMMUNICATION

CONSTANTINE Katsinis
Journal of interconnection networks, v 4(1), pp 77-102
Mar 2003
DOI: https://doi.org/10.1142/S021926590300074X

Abstract

Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. This paper examines the performance of distributed-shared-memory (DSM) systems based on the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) using queuing network models and develops theoretical results which predict processor utilization, message latency and other useful measures. It also presents simulation results which compare the performance of the SOME-Bus, the mesh and the torus using queuing-network models. The SOME-Bus is a low-latency, high-bandwidth, fiber-optic interconnection network which directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. It contains a dedicated channel for the data output of each node, eliminating the need for global arbitration and providing bandwidth that scales directly with the number of nodes in the system. Each of the N nodes has an array of receivers, with one receiver dedicated to each node output channel. No node is ever blocked from transmitting by another transmitter or due to contention for shared switching logic. The entire N-receiver array can be integrated on a single chip at a comparatively minor cost resulting in o(N) complexity. The SOME-Bus has much more functionality than a crossbar by supporting multiple simultaneous broadcasts of messages, allowing cache consistency protocols to complete much faster. The effect of collective communications due to cache coherence is examined. Results reveal that the performance of the SOME-Bus interconnection network is the least affected by large communication times, compared to the other two architectures considered here. Even in the presence of intense coherence traffic, processor utilization and message latency is much less affected than in the other architectures.

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