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Optimized FPGA implementation of a multi program PCR related measurements system in DVB-T: architecture exploration
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Optimized FPGA implementation of a multi program PCR related measurements system in DVB-T: architecture exploration

C. Mannino, H. Rabah, S. Weber, C. Tanougast, Y. Berviller and M. Janiaut
International journal of electronics, v 93(6), pp 373-383
01 Jun 2006

Abstract

All-digital PLL Architecture exploration PCR related measurements
Measurement of quality of service in digital video broadcasting requires particularly the real-time monitoring of program clock reference (PCR) parameters for all the programs contained within the MPEG-2 transport stream. To achieve this, an all digital solution based on a novel all-digital phase locked loop (ADPLL) was proposed, allowing one to cast off the analog components and then a full FPGA implementation. The complexity of the system increases with the number of programs to be processed and an architectural optimization is then necessary. In this paper, several architectures are explored, considering area and objectives throughout. This exploration is based on hard-ware synthesis and code compilation results of system tasks. Three main cases are studied: hardware parallel implementation; hardware blocs reuse and hardware/software implementation. Experimental results are presented and discussed.

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Engineering, Electrical & Electronic
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